Vol 2 Issue 3 July 2014-September 2014

Abstract: In this paper the circuit in which the light activated by sound turns ON for a short duration When any external sound is heard like claps, dog sound etc. Which gives a feel that occupants have been alerted. The monitoring is done by the microphone which is fitted in a place and generates AC signals, that passes through DC blocking capacitor C1 to the base of transistor BC 549(T1). Along with the transistor T2 that amplifies the sound signals and provides current pulses from the collector of T2. When sound amplifies the sound signals and provides current pulses from the collector of T2. When sound is produced near the condenser mic, tiac1 (BT136) fires, activates, lights and the bulb(B1) glows for about two minutes. Fix the unit lose to the sound monitoring spot, with the lamp inside or outside as desired. This also can be used in some restaurants, hotels, and some kids corners are also for the domestic purposes. Connect the microphone to the sound activated lights circuit using a short length of shielded wire. Close the microphone inside a tube to increase its sensitivity.

Keywords: sound sensor, three state.

Title: SOUND HEARD DIMMING LIGHT CIRCUIT WITH THREE STATES USED FOR DOMESTIC ALERTS, ROOFINGS IN HOTELS, KIDS CORNER

Author: S.Jeneeth Subashini, S.Manoj Kumar, S.Karthick , S.Jayandran

International Journal of Electrical and Electronics Research,

ISSN 2348-6988 (online)

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Abstract: In this work, we propose a new resource allocation scheme that increases the effect of diversity by considering the proportional fairness(PF) even after increasing the number of users in downlink MIMO-OFDMA-CDM (multiple input multiple output-orthogonal Frequency division multiple access-code division multiplexing)systems.In the proposed scheme resources are allocated for one subcarrier group and full code-spreading is done for each user using all sources allocated subcarriers.This increases the frequency diversity effect and also increases the multi-user diversity effect. Also the subcarrier allocation is based on the scheme which is not consider in based on the scheme which is not considered in the conventional OFDMA-CDM schemes. The proposed scheme is tested for 16 users. The improvement performances of BER and capacity are shown through MATLAB simulations.

Keywords: COFDM, frequency diversity, interference cancellation, SISO, spectral efficiency.

Title: Design and Evaluation of Resource Allocation Scheme for Downlink MIMO-OFDMA-CDM Systems

Author: S.JeneethSubashini, D Haripriya, Dr.Dhanasekaran.D

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: The main goal in designing a communication system is to achieve reliable data transmission with as small a transmission power as possible, in other words, a power efficient system with the lowest error probability (bit error rate or frame error rate). Moreover, a higher data rate with a constraint on available bandwidth is another target. LDPC codes can be selected as an excellent coding scheme to achieve the highest reliability transmission. The objective in this paper is to develop a model for LDPC codes using simulation in Matrix laboratory language (MATLAB) on which BER calculations is carried out and to evaluate the performance, for different Eb/N0 levels, by varying the code-length, column weight, number of iterations, code-rate of the LDPC code.

Keywords:  BER v/s Eb/N0, LDPC, Mackay matrix

Title: Performance Evaluation of LDPC Codes With Mackay Matrix

Author: Jasmeen Kaur Bisla, Mandeep Kaur, Kuldeep Sharma

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: Programmable Built-In Self-Test (PBIST) is a programmable testing technique where testing is accomplished without the aid of external hardware. The Repair Analyzer enables the fault bits to do the error correction using Redundancy strategy.  To increase the reliability and yield of embedded memories, many redundancy mechanisms have been proposed. All the redundancy mechanisms bring penalty of area and complexity to embedded memories design. Considered that SRAM is used to configure for different needs, the BISR had better bring no change to other modules in SRAM. To solve the problem, a new redundancy scheme is proposed in this project.  Some normal words in embedded memories can be selected as redundancy instead of adding spare words, spare rows, spare columns or spare blocks. Built-In Self-Repair (BISR) with Redundancy is an effective yield-enhancement strategy for embedded memories. This  project  proposes  an  efficient  BISR  strategy  which  consists  of  a Programmable  Built-In  Self-Test (PBIST) module, a Built-In  Address-Analysis (BIAA) module, Multiplexer (MUX) module and a SRAM module. The BISR is designed flexible that it can provide four operation modes to SRAM users. Each fault address can be saved only once is the feature of the proposed BISR strategy. In BIAA module, fault addresses and redundant ones form a one-to- one mapping to achieve a high repair speed. Besides, instead of adding spare words, rows, columns or blocks in the SRAMs, users can select normal words as redundancy, since it supports word-oriented memories.

Keywords: Programmable Built-In Self-Test (PBIST), Built-In Address-Analysis (BIAA), Multiplexer (MUX), SRAM, full repair analyzer.

Title: Programmable Built In Self Test and Repair Analyzer Using Redundancy for Word Oriented SRAM

Author: Soni Mishra, Sandeep Sunkari

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract:  This paper presents a new method to solve the network reconfiguration problem in the presence of distributed generation (DG) with an objective of minimizing real power loss and improving voltage profile in distribution system. A meta heuristic Harmony Search Algorithm (HSA) Algorithm is used to simultaneously reconfigure and identify the optimal locations for installation of DG units in a distribution network. Sensitivity analysis is used to identify optimal locations for installation of DG units and also Different scenarios are used. The constraints of voltage and branch current carrying capacity are included in the evaluation of the objective function. Here both HSA and PSO methods are used that has been tested on 33-bus and 69-bus radial distribution systems at three different load levels to demonstrate the performance and effectiveness of the HSA and PSO methods. The results obtained are encouraging.

Keywords: Distributed generation, distribution system, Harmony Search Algorithm, Particle Swarm Optimization Algorithm, real power loss, reconfiguration, voltage profile.

Title: Optimal Network Reconfiguration and Loss Minimization Using Harmony Search Algorithm In The Presence Of Distributed Generation

Author: Pardhavi Sai Sree.T, Poorna Chandra Rao.N

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: This paper deals with an alternative proposition for the steady state modeling of unified power flow controller (UPFC). Since current limitations are determinant to FACTS apparatus design, the proposed current based model (CBM) assumes the current as variable, allowing easy manipulation of current restrictions in optimal power flow evaluations. The performance of the proposed model and of the power injection model (PIM) are compared through a Quasi-Newton optimization approach. Two operating situations of a medium size network with 39 busbars were studied from the point of view of optimization and current limits, observing the performance of the UPFC modelling.

Keywords: FACTS, optimal power flow, Quasi-Newton method, UPFC.

Title: POWER FLOW CONTROL BY USING UPFC BASED QUASI-NEWTON OPTIMIZATION IN A DISTRIBUTION SYSTEM

Author: Poornima Reddy A, Hari T

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: Digital Signal Processing is the mathematical handling of an information signal to modify or improve it. Digital Signal Processors are microprocessors specially designed to handle Digital Signal Processing tasks. These devices have seen tremendous growth in the last decade, finding use in everything from cellular telephones to advanced scientific instruments. In fact, hardware engineers use “DSP” to mean Digital Signal Processor, just as algorithm developers use “DSP” to mean Digital Signal Processing. DSP has become a key component in many consumers, communications, medical, and industrial products. This paper illustrated the role of Digital Signal Processors (DSP) for fourth generation mobile systems. The currently deployed wireless infrastructure supports the fourth generation of these standards is nearly impossible with respect to the cellular base station. Many solutions for base station or mobile station have been implemented over the years, and each solution required a combination of two components, ASICs (Application Specific Integrated Circuits), and DSPs (Digital Signal Processors). This two-chip solution partitions the processing tasks between the ASIC and DSP, respectively. Although this solution is functionally acceptable, its system cost and flexibility are not completely optimized. Global objectives and attributes that include worldwide roaming, universal connectivity, high data transmission rates, location service capability ,and support for high-quality multimedia services are now required.

Keywords:  Digital Signal Processors, 4G Mobile Communications Systems.

Title: The role of digital signal processors (DSP) for 4G mobile Communication systems

Author: Raushan Kumar, Sourabh Kumar, Yogesh Rana

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: these topic basically illuminates to develop the protection system for inverters using pic controller. The current system consists of mosfet for the high power inverters and according to the simulation results hardware implementation is done with controller board. For the reference values for pic code generation, and if any fault occurs in the system then the system will be protected. Pic board can be interface with the hardware and in software of pic program can be developed for the feedback of the protection system. However the system which can be developed in hardware or power circuit can be modify also with other power ratings and according to that pic controller will work and the system for the protection of the power inverters can be easily done.

Keywords:  PIC Controller, Peak Amplitude, Conducting Current, Power Factor

Title: Analysis of MOSFET Based Inverter Protection System Using PIC Controller

Author: Harshil Shah

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract:  In recent times, many existing and developing electrical and electronic fields require voltages of different levels supplied from a singular existing source voltage such as a battery. Basically DC converters are devices designed for the purpose of changing DC voltage levels. The converters are electronic devices, it has an output voltage magnitude that is either greater than or less than the input voltage magnitude. Rising energy has a higher cost of delivering power and low power density. Meanwhile, the demand for compact power supplies rises significantly. It requires power supplies with high efficiency, low cost and smaller size. In order to control the output voltage of the converter, the controller is designed to change the duty cycle of the converter. In this converter IGBT switch is digitally controlled by microcontroller. In this work simulation and then hardware implementation is done with analysis of the results. The converter is mainly used, where load is very sensitive (battery - powered products), it provides variation of 1% only.

Keywords: Micro Controller, Switch Voltage, Power Factor, PWM Pulses.

Title: Design and Analysis of DC To DC Buck-Boost Converter System with Inter Phase of Micro Controller

Author: Shuchi Shah

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: Wired networks exist between a number of devices connected to each other using connecting media, such as cables and routers. Wired networks can be applied within an area limited by the cables and routers that allow for sending and receiving of data. Wireless networks, on the other hand, are free of such space limitations and are more easily able to connect different devices to each other. Wireless nodes can play the roles of both hosts and routers, which forward the packets to neighboring nodes. In recent days, wireless networks are mostly used than wired networks. The reasons for using wireless networks are cost effectiveness of network deployment and its applicability to environments where wiring is not possible or it is preferable solution compared with wired networks. When designing wireless networks and/or studying their behaviour under various conditions, software simulation tools are often used.

Keywords: Wired networks, wireless networks.

Title: Implementation of Wired and Wireless Networks, Analysis Simulation and Result Comparison Using Ns2

Author: S. Jeneeth Subashini, D. Guna Shekar, C.Harinath Reddy, M. Manikanta

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: In Industry nowadays the control of chemical process is important task. Mostly all the chemical processes are highly nonlinear in nature and this causes instability of process. Continuous Stirred Tank Reactor (CSTR)   is   an important subject in chemical process and offering a diverse range of researches in the area of the chemical and control engineering. In this paper the design of a nonlinear feedback controller is analyzed for temperature control of continuous stirred tank reactors (CSTR) which have strong nonlinearities. Here Particle Swarm Optimization (PSO) algorithm based PID controller tuning is attempted for the temperature control of Continuous Stirred tank reactor (CSTR), Based on the Performance indices and optimization criterion controller can   be estimated. The Integral Square Error (ISE) criterion is used to guide PSO algorithm to search the controller parameters like   Kp ,  Ki , Kd . A comprehensive simulation is carried out with PID and GA controller Structures. The simulation results show that the PSO based PID controller tuning approach provides better performance compared to other conventional PID tuning methods.

Keywords: PID controller, Particle Swarm Optimization Algorithm (PSO), Genetic algorithm (GA) Stochastic systems, CSTR.

Title: TEMPERATURE CONTROL OF CSTR - A COMPARATIVE APPROACH

Author: Indu yadav, Dr. Anurag Trivedi

International Journal of Engineering Research and Reviews

ISSN 2348-697X (Online)

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Abstract:  In Industry nowadays the control of chemical process is important task. Mostly all the chemical processes are highly nonlinear in nature and this causes instability of process. Continuous Stirred Tank Reactor (CSTR) is an important subject in chemical process. Therefore various control approaches have been applied on CSTR to control its parameters.  Here Particle Swarm Optimization (PSO) algorithm based PID controller tuning is attempted for the temperature control of Continuous Stirred tank reactor (CSTR), Based on the Performance indices and optimization   criterion controller, can   be estimated. The Integral Square Error (ISE) criterion is used to guide PSO algorithm to search the controller parameters like K p, K _i, K _d . The main focus of this paper is to apply soft computing technique that is PSO to design and tuning of PID controller to get better dynamics and static performance at the output .The simulation results show that the PSO based PID controller tuning approach provides better performance compared to the conventional PID controller.

Keywords: PID controller, Particle Swarm Optimization Algorithm, Stochastic systems, CSTR.

Title: Temperature Control of CSTR Using New Particle Swarm Optimization Algorithm

Author: Indu Yadav, Dr. Anurag Trivedi

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: Paper shows the implementation of improved Radix 4 Booth multiplier in VHDL software. Booth multiplication allows for faster, smaller multiplication circuits through encoding the signed numbers to its 2’s complement and which is also one of the standard technique used in chip designing. The algorithm reduces the number of partial product to half over “long multiplication” techniques. Proposed optimized Radix-4 Booth’s multiplier modify the way it does the addition of partial products. All these multiplier designs were modelled in Verilog HDL. Paper presents comparative analysis of Radix-4 booth multiplier with different multiplier techniques. Comparison shows optimized Radix-4 multiplier is superior from other multipliers in terms of various constraints.

Keywords: Booth’s algorithm, Radix-4 booth, Radix-2 multiplier, Vedic multiplier, Bypass multiplier, Shift and Add multiplier.

Title: COMPARATIVE ANALYSIS ON POWER AND DELAY OPTIMIZATION OF VARIOUS MULTIPLIERS USING VHDL

Author: Shubhi Shrivastava, Pankaj Gulhane

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: Field Programmable Gate Array (FPGA) provides breakout performance capacity and system integration while optimizing to improve FPGA devices based on CAD tools in the Verilog Hardware Description Language (VHDL), which demonstrate the logic, function and behaviors of system hardware. State machines are often the backbone of FPGA development. Choosing the right architecture and implementation methods will ensure that an optimal solution can be obtained.  For a designer, the best way to address these actions and sequences is by using a state machine. State machines are logical constructs that transition among a finite number of states. A state machine will be in only one state at a particular point in time. It will however, move between states depending upon a number of triggers. This paper mainly focuses on the design of Moore and Mealy state machine in FPGA. RTL logic has been adopted for designing purposes. The minimum time period, maximum delay, less number of flip flops, registers etc. have been considered to design the proposed Moore and Mealy state machines more effectively. 

Keyword: Finite state machine, Moore state machine, Mealy state machine, State transition, Sequential systems, Time delay, Test bencher, Xilinx ISE simulator.

Title: VHDL IMPLEMENTATION OF MOORE AND MEALY STATE MACHINE

Author: Md. Mehedi Hasan, Prajoy Podder, Jag Mohan Thakur, Anamul Haque, Mursalin Sayeed, Md. Rafiqul Islam

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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Abstract: In the last decade, Orthogonal Frequency Division Multiplexing (OFDM) based communication systems have been identified as one of the key transmission techniques for next generation wireless communication systems. The main objective is to transmit the OFDM signal with low bit error rate in the noisy environment.  A cyclic prefix acts as a buffer region where delayed information from the previous symbols can get stored. Different modulation technique with respect to bit-error rate and SNR ratio is analyzed using MATLAB software. Here the performance of OFDM signal is analyzed by comparing the BER results of coding technique such as convolution [1]. As well various modulation methods are also used. Two decoding methods are used to analyze the signal. One is soft decoding and other is hard decoding with convolution code. Three types of modulation methods are used with normal OFDM to analyze the system performances which are Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), and Quadrature Amplitude Modulation (QAM)[2]. The goal of this paper is to improve system performance by the mean of low bit error rate. Finally bit error rate of these three methods are analyzed by comparing SNR versus BER plots. Soft decoding method in convolution with high code rate gives better BER performance.

Keywords: OFDM, Convolution Code, Error detection, Error correction code, cyclic prefix, SNR, QPSK, BPSK, QAM, and BER.

Title: BER IMPROVEMENT IN OFDM USING CODING TECHNIQUES

Author: Mrs. Shubhangi S. Joshi, Mrs. A. P. Laturkar

International Journal of Electrical and Electronics Research

ISSN 2348-6988 (online)

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