Abstract: In a VLSI circuit, interconnection plays the dominant role in every part of the circuit nearly 70 percent of the area depends on interconnection, 20 percent of the area depends on insulation, and remaining 10 percent to devices. The binary logic is limited due to interconnect which occupies a large area on a vlsi chip. In this work, the designs of quaternary-valued logic circuits have been explored over multi-valued logic due to the following reasoning. An approach to mitigate the impact of interconnections is to use multiple-valued logic (mvl) , hence, more information can be carried in each wire, reducing the routing network. Therefore, a single wire carrying a signal with n logic levels can replace [log2n] wires carrying binary signals. Reducing the routing leads to a direct reduction of the line capacitance and the overall circuit area. Therefore, this results in increasing the maximum operation frequency and also reducing the power consumption. The most important characteristics of this method are a voltage-mode structure .voltage mode structure has the advantages like reduced power consumption implemented in a standard cmos technology. Our new method overcomes convectional techniques with simple and efficient cmos structures.
Keywords: multiple-value logic, quaternary logics, look- up tables, fpgas, standard cmos technology
Title: A NOVEL VOLTAGE-MODE LUT USING CLOCK BOOSTING TECHNIQUE IN STANDARD CMOS
Author: Mr. J. ILANTHENDRAL, SATHYAVATHI N S
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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