Analysis of Radix-2^2 SDF Pipeline FFT Architecture in VLSI Using Chip Scope

G. Mohana Durga, D.V.R. Mohan

Abstract: Pipelined Fast Fourier Transform (FFT) architectures are efficient for long instances in digital communication. For long instances, Single-Path Delay-Feedback (SDF) FFT architectures minimize required memory, which can dominate circuit area and power dissipation. This paper discusses about the architecture of Radix- Single Delay Feedback for N = 1024 samples and its implementation. Then the code is dumped into Xilinx Spartan 3E kit to analysis Radix- SDF architecture by using chip scope. Radix- SDF algorithm has the same multiplicative complexity as radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm. Simulation and Synthesis are carried on Modelsim 6.3 and Xilinx ISE 12.2. The design has been coded in Verilog [6] and targeted into Xilinx Spartan3E FPGA kit.