Abstract: In this paper, A Novel high speed Analysis of SRAM circuit that employs adiabatic charging of a word line during a read operation was found to provide a large dynamic noise margin (DNM) for reading and CAM memory by using a reordered overlapped search mechanism for high-throughput low-energy. In our circuit implementation in CAM memory cell, each word circuit is independently controlled by a locally generated timing signal rather than a global signal. In SRAM an analysis of the time-wise change in DNM revealed that the read noise margin of this circuit was 1.9 times larger than that of a conventional two-BL circuit. But in asynchronous CAM operates 5.98 times faster than a synchronous CAM with 14.2% smaller energy dissipation.
Keywords: Adiabatic, low power, asynchronous circuits, associative memory, NAND-type CAM, RWOS, POP.
Title: Analysis of SRAM and High Speed CAM Based On Reordered Overlapped Search Mechanism
Author: P. Ananthajothi, L. Revathy
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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