Abstract: The communication mechanism is employed in system on a single chip is an important contribution to their overall performance. The data bus based mechanism is applied in many areas of real time applications of Socs realizing on FPGA due to its flexibility and simplification in designing tool. It challenging task in a network-on-chip to design an on-chip switch / router to support (hard) guaranteed throughput under very tight on-chip constraints of power, timing, area and time-to-market. This paper presents an on-chip network to support traffic permutation in multiprocessor SoC applications. The proposed network employs a pipelined circuit switching approach combined with a path-setup scheme under a multistage network topology. The circuit-switching approach offers a guarantee of permuted data and its compact overhead enables the benefit of stacking multiple networks with saving power and area. The proposed design is develop using Xilinx 9.1ISE, Simulated on modelsim 6.3f and implemented on Spartan 3 device.
Keywords: Multistage Interconnection Network, Network-on-chip, Traffic permutation network, Circuit Switching, Dynamic path setup scheme, and system- on-chip and Network topology.
Title: Design and FPGA Implementation of On-Chip Network Topology with Port Addressing Scheme for Permutation Network
Author: Umadevi R., Sandhya Rani M.H., B.N. Shobha
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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