Abstract: In this paper we present a high-performance, high throughput, and area efficient architecture for AES algorithm. The sub keys, required for each round of the Rijndael algorithm, are generated in real-time by the key scheduler module by expanding the initial secret key, thus reducing the amount of storage for buffering. The AES algorithm is a symmetric block cipher that can encrypt (encipher) and decrypt (decipher) information.
AES has a fixed block size of 128 bits and a key size of 128, 192 or 256 bits, whereas Rijndael can be specified with key and block sizes in any multiple of 32 bits, with a minimum of 128 bits and a maximum of 256 bits. AES operates on a 4×4 array of bytes, termed the state. For encryption, each round of AES (except the last round) consists of four stages. a) Sub Bytes - a non-linear substitution step where each byte is replaced with another according to a lookup table (known as S Box). b) Shift Rows - a transposition step where each row of the state is shifted cyclically a certain number of steps. c) Mix Columns - a mixing operation which operates on the columns of the state, combining the four bytes in each column using a linear transformation. d) Add Round Key - each byte of the state is combined with the round key; each round key is derived from the cipher key using a key schedule.
Title: Design and Implementation of AES Algorithm for Complex Encryption and Decryption
Author: CH.SALA ANKARAJU, M.A.VIJAY KAMALNATH
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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