Abstract: This paper design and simulation of 1Kb memory using memory bank technique. To get required frequency of operation efficient peripherals has to be designed, since the memory core exchanges performance and reliability for diminished area, memory plan depends exceedingly on the peripheral hardware to recuperate both speed and electrical integrity.. In this section we discuss the row decoders, word line drivers, pre-charge circuit, column multiplexers/Decoders, Sense amplifiers and write drivers [14]. Figure1 shows the monolithic peripheral circuitry of 1Kb SRAM Based memory. Generally for Smaller memory designs monolithic architectures are preferred, but in the Design of bigger memories monolithic architecture will not give efficient performance. The frequency of operation of the circuit is reduced by a factor of two as the number of rows doubles. Similarly the frequency of memory, reduced by a factor of four as the number of columns doubles, hence in bigger memory designs memory portioning technique is used which is known as memory banking.
Keywords: Architecture, capacitances, delays, monolithic, memory banking.
Title: Design and simulation of 1 Kb memory and its peripherals
Author: Prithviraj Singh Chouhan, Dr. D.K. Panda
International Journal of Interdisciplinary Research and Innovations
ISSN 2348-1218 (print), ISSN 2348-1226 (online)
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