Abstract: This paper describes a system of AES algorithm in optimized manner. The Advanced Encryption Standard can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker, more optimized solution. This design includes the AES algorithm with regard to Area optimized software model by using the Very High Speed Integrated Circuit Hardware Description language (VHDL). Xilinx ISE project Navigator 14.1 software is used for simulation and optimization of the synthesizable VHDL code. The National Institute of Standards and Technology (NIST) has initiated a process to develop a Federal information Processing Standard (FIPS) for the Advanced Encryption Standard (AES), specifying an Advanced Encryption Algorithm to replace the Data Encryption standard (DES) the Expired in 1998. All the transformations of both Encryptions and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption. The project is designed by reducing the number of slices in Software AES model, the area optimized AES-128 Bit structure produced by this project which gives most optimized structure as compared with previous results.
Keywords: ASIC Application Specific Integrated Circuits, AES Advanced Encryption Standard, ASIP Application Specific Instruction Processor, CLB Configurable Logic Blocks, CBC Cipher Block Chaining.
Title: DESIGN OF AES ALGORITHM IN OPTIMIZED MANNER ON FPGA
Author: Hrushikesh S. Deshpande, Kailash J. Karande
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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