Abstract: The real numbers represented in binary format are known as floating point numbers. Based on IEEE-754 standard, floating point formats are classified into single precision and double precision. The advantage of floating-point representation over fixed point representation is that it can support a much wider range of values Floating point multipliers are key components of many high performance systems such as FIR filters, Microprocessors, Digital Signal Processors etc. Hence, this project aims to design a 64-bit double precision floating point multiplier by using vedic multiplication. Vedic multiplier is a special kind of multiplier which is capable to multiply more number of bits at a time, at faster rate than conventional multiplier. The proposed multiplier can be designed using Verilog HDL and it is implemented on a Xilinx ISE 14.3 tool targeting the Spartan device.
Keywords: Single Precision, Double Precision, Field Programmable Gate Array, Multiplier, Vedic multiplier, Urdhava Triyagbhyam.
Title: Design of Double Precision Floating Point Multiplier Using Vedic Multiplication
Author: D.Heena Tabassum, K.Sreenivas Rao
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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