Abstract: The demand for power-sensitive design has grown significantly in recent years due to tremendous growth in portable applications. Consequently, the need for power efficient design techniques has grown considerably. Several efficient design techniques have been proposed to reduce both dynamic as well as static power in state-of-the-art VLSI circuit applications. With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Clock power is significant in high-performance processors. Clock gating is very useful for reducing the power consumed by digital systems. Three gating methods are known. The most popular is synthesis-based, data-driven method and auto-gated FFs (AGFF).This paper presents a novel method called Look-Ahead Clock Gating (LACG), which combines all the three. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. The low leakage FFs are designed using sleep transistors and simulated in tanner design environment using 90 nm and 45n technology files.
Keywords: Clock gating, Static power, Leakage power, Sleep transistors.
Title: Enhanced Auto-Gated Flip-Flop Using Clock Gating Technique with Sleep Transistor
Author: M.Saranya, P.Muthukumaran
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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