Abstract: Historically system design approaches favored the use of digital signal processors to implement controllers for embedded systems. Processor based implementation lack the speed advantage offered by custom hardware and concurrent processing because of their sequential nature. In some applications using a DSP would be overkill in design, and other approaches need to be explored. Custom hardware is an option where in the implementation could be done using FPGA, ASIC or an SoC. FIRs are a major component of signal processing applications and the design and implementation in FPGA of sigma 1 controller for semiactive suspension is presented in this paper. Alternate architectures for multiplication are explored and results are presented. Since multiplication by constant coefficients is needed for FIR implementation CSD notation is employed which minimizes the number of non-zeros in the constant multiplier. The results indicate area savings up to 74% and improvement is speed of computation by 7.2 times. Further research in this area needs to explore the possibility of using transposed form of FIR structure and possibility of optimization in resources consumed.
Keywords: velocity estimation, FIR filters, CSD, multiplier, shifter.
Title: FPGA Based Optimized Implementation of Control Algorithm for Semi-active Suspension Systems
Author: Sanjay Eligar, R M Banakar
International Journal of Interdisciplinary Research and Innovations
ISSN 2348-1218 (print), ISSN 2348-1226 (online)
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