Abstract: Recently images comprise a heavy part of future wireless data. Arising mobile devices and wireless sensors require algorithms that get along with the representation of the input data in a proper form for storage and transmission. One approach to diminish this problem is to eliminate redundant information from the transmitted images or frames data over the wireless channel through image compression techniques. However current software performance disregards the time and resources throughout compression and RF wireless transmission. Though, these efforts fall short of meeting real-time processing requirements.In this paper flexible hardware architecture of multi-level decomposition Discrete Wavelet Transform (DWT) has proposed for image compression application. This architecture of DWT decomposition is described and synthesized with VHDL based methodology. The design can be achieved on any targeting FPGA device with slight changes. It facilitates every size of image and any level of decomposition. In order to reduce computational complexities Haar wavelet has been used. The competed size utilization of this 2D DWT multilevel core can be used to counter severe hardware constraints of various wireless and mobile devices applications.
Keywords: 2D DWT, Linear algebra of DWT, Haar wavelet, VHDL, FPGA.
Title: Hierarchical Hardware Architecture of Discrete Wavelet Transform For Image Compression
Author: Khamees Khalaf Hasan, Umi Kalthum Ngah, Mohd Fadzli Mohd Salleh
International Journal of Computer Science and Information Technology Research
ISSN 2348-120X (online), ISSN 2348-1196 (print)
Research Publish Journals
