Abstract: This work presents the design and characterization of 6 full adder circuits in a 50-nm technology. This Based on the logic function realized, the adders have been characterized for performance area and power consumption. The impact of sum and carry propagation delays on the performance, power of these systems have been evaluated. The study of the above work has been carried using Micro wind 3.1 CAD tool with detailed transistor level simulations in a 50-nm technology process.
Keywords: Full adders, Power Delay, Power dissipation, area.
Title: Impact of Logic and Circuit Implementation on Full Adder Performance in 50-NM Technologies
Author: Mahesh Yerragudi, Immanuel phopakura
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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