Abstract: A huge portion of the on chip power is stimulated by the clock system which is made of the clock distribution network and flop-flops. In synchronous systems, high speed has been achieved using sophisticated pipelining techniques.
In this scrutiny we introduce a new Dual dynamic node hybrid flip-flop and a novel embedded logic module based on DDFF. These flip-flops are based on the D flip-flop and latch embedded logic. This logic uses basic gates and universal gates and also Comparing the performance of DDFF with other Flip-flops which are designed for low power and high performance. The basic features of these flip-flops are highlighting and appraise them based on power consumption, speed. The foremost aim is an AND function is removed from the critical path to facilitate a faster discharge operation. Instead of this we are using a simple two transistor AND gate design is used for the reduction of complexity.
To introduce the conditional pulse enhancement for speed up the discharge swing along the critical path only when needed. For saving the power we can reduce the transistor sizes which are used at delay inverter and pulse generation circuit.
Keywords: Embedded logic, flip-flops, high-speed, leakage power, low-power.
Title: Implementation of an Efficient Pulse-Triggered Flip Flop for Ultra Applications
Author: Narayana.Ramu, M.A.V. Kamal Nath
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
Research Publish Journals
