Abstract: This paper presents a low power, low cost design of PLL (Phase Locked Loop).The proposed PLL comprises of PFD(Phase frequency Detector),CP(Charge Pump), Second order low pass filter as a loop filter and CS-VCO(Current starved- Voltage control Oscillator). The VCO used for the designed. PLL shows higher tuning range i.e. 156MHz- 169.73MHz with low power consumption of 5.55mW, also it is designed such that, it eliminate the function of frequency divider circuit to some extent . The proposed PLL circuit is designed and simulated on Generic 250nm CMOS technology.
Keywords: PLL, PFD, CP, VCO, CS-VCO, CMOS, Power consumption.
Title: Implementation of five-stage CS-VCO circuit on 250nm CMOS Technology for Low Power Digital Applications
Author: Renu Prabha Sahu, Ashish Tiwari
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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