Abstract: Minimizing power consumption is vitally important in modern circuit designs. The internal components should be designed in such a way that they consume low power with high speed. Flip flops are the storage elements in all digital design but, consume much power due to static and dynamic power dissipation and clock skew. The main idea is to introduce the design of high performance pass transistor flip flop which acquires less area and transistor count. In the existing method, an extremely low power flip flop named topologically compressed flip flop is proposed. As compared with conventional type FFs, the FF reduces power dissipation by 75% at 0% data activity. The reduction is achieved by merging the logically equivalent transistors to the unconventional latch structure. In order to reduce the transistor count and power consumption, a new method static pass transistor logic (SPTL) is introduced. The SPTL will be reducing the transistor count and power dissipation. The high performance of SPTL is designed and the simulation has been carried out on Tanner EDA Tool. An experimental chip design with 40 nm CMOS technology shows that almost all conventional FFs are replaceable with proposed FF while preserving the same system performance and layout area.
Keywords: Flip flops, transistors, low power.
Title: Low Power D Flip Flop Using Static Pass Transistor Logic
Author: T.SURIYA PRABA, R.MURUGASAMI
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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