Abstract: Increased usage of battery operated portable devices demands VLSI and ultra large scale integration (ULSI) designs with an improved power delay characteristics. Full adder being one of the most fundamental building block of all the circuit applications. A 1-bit full adder design employing both complementary metal oxide semiconductor (CMOS) logic and transmission gate logic is designed. The circuit was implemented for a single bit using tanner tool in 180nm technology and the parameters such as power and delay were compared with the existing designs of complementary pass transistor logic (CPL), transmission function adder (TFA), transmission gate adder (TGA), Hybrid pass logic with static CMOS output drive full adder (HPSC) and so on. For 180nm technology, the average power consumption was found to be extremely low with moderately low delay resulting from the deliberate incorporation of very weak CMOS inverters coupled with the strong transmission gates. The same design can further extend for implementing 32 bit full adder also. The present implementation was found to offer significant improvement in terms of power and speed.
Keywords: CMOS, TGA, CPL, HPSC, TFA.
Title: Performanance Analysis of a 1-Bit Full Adder Using 180nm Technology
Author: M. HEMALATHA, A. NIVETHA, B. NANDHINI
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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