Abstract: This paper presents algorithms and architecture designs that can meet real-time requirements of for several user channel estimation and detection in code-division multiple-access-based wireless base-station receivers. Entangled algorithms proposed to implement several user channel assessment and demodulation make their real-time execution difficult on current digital signal processor-based receivers. A maximum-likelihood based several user channel assessment scheme requiring matrix conversion is draft again from an demodulation perspective for a reduced intricacy, repetitive scheme with a simple fixed-point very large scale integration (VLSI) architecture. A reduced-intricacy, bit-streaming several user demodulation algorithm that avoids the need for multishot demodulation is also developed for a simple, pipelined VLSI architecture. Thus, we develop real-time solutions for several user channel assessment and demodulation for third-generation wireless systems by: 1) designing the algorithms from a fixed-point execution perspective, without significant loss in error rate performance; 2) task partitioning; and 3) designing bit-streaming fixed-point VLSI architectures that explore pipelining, correspondence, and bit-level computations to achieve real-time with minimum area overhead.
Keywords: Digital signal processor, several user channel estimation, several user detection, real-time exe. very large scale integration, wideband code-division multiple-access.
Title: Real-Time Algorithms and Architectures for Several User Channel Detection in Wireless Base Station Receivers
Author: Nitish Meena, Dr. Nilesh parihar
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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