Abstract: Memories are affected by errors in radiation environment it causes data corruption. Some of the error correcting codes are widely used to protect the memory from the errors but the main disadvantage is this codes make encoder, decoder very complex and lead to delay and area overhead, so to maintain the memory reliability, it necessary to protect memory by using protection codes. Decimal Matrix Code (DMC) is used to correct the error in the memory, protect the memory from the Multiple Cell Upset (MCU) and it maintain the memory reliability. This coding technique is maximize the error correction capability, this is the advantage of this code, and it uses Encoder Reuse Technique (ERT) to minimize the area overhead. ERT uses DMC encoder to be a part of decoder and it reduces the redundant bits.
Keywords: Multiple Cell Upset (MCU), Decimal Matrix Code (DMC), Encoder Reuse Technique (ERT), Memory.
Title: REDUCING REDUNDANT BITS AND ENHANCED MEMORY RELIABILITY USING DECIMAL MATRIX CODE
Author: V.Vithya, Dr. P. Sakthivel
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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