Abstract: The clos networks are the class of multistage switching network topologies that provide alternate paths between inputs and outputs. It is one of the known connection networks in processing system and distributed Systems, which are extensively used in many fields such as telecommunication networks, ATM switches and data transmission. One of the key challenges in designing a clos network switch for a high speed environment is designing the architecture switch module and arbitration algorithms so as to provide wide range of traffic patterns and resolve contention between the stages of the switches in clos network. So efficient various routing algorithms and different techniques are proposed to solve problem which occur in clos network and also to achieve guaranteed throughput, latency, bandwidth, power and area parameters. In this paper, different techniques and routing algorithms for a clos permutation network are reviewed.
Keywords: Multistage interconnection networks (MINs), clos Network , parallel routing, rearrangeable ,non-blocking, Blocking, permutation network, Clos network on chip (CNOC), Buffer less clos network (BLOCON), Network-on-chip (NOC).
Title: Review of On-Chip Network Topology for Clos Permutation Network
Author: Umadevi R., Sandhya Rani M.H., B.N. Shobha
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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