Abstract: Field Programmable Gate Array (FPGA) provides breakout performance capacity and system integration while optimizing to improve FPGA devices based on CAD tools in the Verilog Hardware Description Language (VHDL), which demonstrate the logic, function and behaviors of system hardware. State machines are often the backbone of FPGA development. Choosing the right architecture and implementation methods will ensure that an optimal solution can be obtained. For a designer, the best way to address these actions and sequences is by using a state machine. State machines are logical constructs that transition among a finite number of states. A state machine will be in only one state at a particular point in time. It will however, move between states depending upon a number of triggers. This paper mainly focuses on the design of Moore and Mealy state machine in FPGA. RTL logic has been adopted for designing purposes. The minimum time period, maximum delay, less number of flip flops, registers etc. have been considered to design the proposed Moore and Mealy state machines more effectively.
Keyword: Finite state machine, Moore state machine, Mealy state machine, State transition, Sequential systems, Time delay, Test bencher, Xilinx ISE simulator.
Title: VHDL IMPLEMENTATION OF MOORE AND MEALY STATE MACHINE
Author: Md. Mehedi Hasan, Prajoy Podder, Jag Mohan Thakur, Anamul Haque, Mursalin Sayeed, Md. Rafiqul Islam
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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