Abstract: This project is primarily deals the construction of 16 bit high speed on adder. The motivation behind the investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance of Central Processing Unit (CPU) . In this research article, we will present fast 16 bit adder with some approximation technique which is used in arithmetic application. For application analysis i am using edge detection where i am using my proposed Adder. Using this application i will prove that proposed adder having very less error which is tolerable by human eye. This project is design on Xilinx-14.1 and simulated on Modelsim. Application analysis will be done on Matlab for the application of Sobel edge detection. Image quality analysis will be done by PSNR, SSIM, FSIM and RFSIM.
Keywords: Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), PSNR, SSIM, FSIM and RFSIM, VLSI.
Title: VLSI Implementation of High Speed 16 Bit Adder for Image Processing Application
Author: Parul Jaiswal, Rahul Gedam
International Journal of Electrical and Electronics Research
ISSN 2348-6988 (online)
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